This invention relates generally to solid state switches and more particularly, it relates to an improved solid state switch which has the capability of retaining its last state memory in the event of a power failure or interruption.
A prior art search directed to the subject matter of this application in the U.S. Patent and Trademark Office revealed the following U.S. Letters Patent:
4,035,668 PA0 4,521,693 PA0 4,649,302 PA0 4,851,721 PA0 4,859,875
In U.S. Pat. No. 4,035,668 to Shunji Minami et al. issued on Jul. 12, 1977, there is disclosed an electronic input-interruption timer which includes an input resistor, a capacitor, a switching element, a MOS field-effect effect transistor, a discharge resistor and a switching circuit. The switching circuit is operable in response to the magnitude of the drain current of the field-effect transistor so that it is turned off after a time delay in case of an input power interruption. In U.S. Pat. No. 4,851,721 to Takenori Okitaka issued on Jul. 25, 1989, there is disclosed an interconnection circuit of a semiconductor integrated circuit connected between a first circuit for applying an input signal and a second circuit for outputting an output signal which includes a delay means formed of a resistance 7 and a parasitic capacitance 26. The delay means functions to apply an overvoltage supplied to the input 8, which receives the input signal from the first circuit, to a processing means with a delay.
In U.S. Pat. No. 4,859,875 to Jenoe Tihanyi et al. issued on Aug. 22, 1989, there is taught an optocoupler which includes a power FET 1 driven by a photodiode chain 9 across a switch that has two FETs 5 and 6 arranged in series. The photodiode chain 9 is optically coupled to a light-emitting diode 10. Upon illumination of the photodiode chain 9, the first FET 5 is driven into conduction which permits current to flow from a capacitor C connected to a fixed voltage into the gate-source of the power FET 1 and switches on rapidly the same. Upon cessation of the illumination, the second FET 6 is driven into conduction which discharges the gate-source capacitance of the FET 1. As a result, the power FET 1 is blocked.
U.S. Pat. No. 4,649,302 to Michael A. Damiano et issued on Mar. 10, 1987, discloses a solid state switch for controlling a load supplied from either an alternating current or a direct current power supply line. The switch includes a pair of field-effect transistors FET 1 and FET 2 and a common control circuit for applying turn-on signals to the field-effect transistors. The control circuit further includes an opto-isolated logic signal input circuit formed of a light-emitting diode and a phototransistor. U.S. Pat. No. 4,521,693 to Alan L. Johnson issued on Jun. 4, 1985, teaches an optically-coupled/isolated electronic single pole, double throw power relay switch which includes two gate-controlled bidirectional thyristors (triacs).
However, none of the prior art uncovered in the search disclosed a solid state switch which has the capability of retaining its last state memory in the event of a power failure like that of the present invention which includes an output driver formed of an N-channel MOS field-effect transistor, a holding capacitor having its one end connected to the gate of the field-effect transistor and the other end connected to a ground potential, and means interconnected between a power supply voltage source and the other end of a charging resistor for preventing leakage of the holding capacitor.